Fundamental Circuit Topology of Duo-Active-Neutral-Point-Clamped, Duo-Neutral-Point-Clamped, and Duo-Neutral-Point-Piloted Multilevel Converters

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dc.contributor.authorDargahi, Vahida
dc.contributor.authorAbarzadeh, Mostafab
dc.contributor.authorCorzine, Keith A.
dc.contributor.authorEnslin, Johan H.
dc.contributor.authorSadigh, Arash Khoshkbar
dc.contributor.authorRodriguez, Jose
dc.contributor.authorBlaabjerg, Frede
dc.contributor.authorMaqsood, Ati
dc.date.accessioned2022-10-07T15:31:35Z
dc.date.available2022-10-07T15:31:35Z
dc.date.issued2019-06
dc.descriptionIndexación: Scopuses
dc.description.abstractMultilevel voltage-source converters are well-suited for power conversion applications demanding higher power density, reliability, efficiency, and power quality. An unremitting and persistent research for developing advanced multilevel converter topologies with improved characteristics, performance, modulation techniques, and control methods continues. This paper proposes duo-neutral-point-clamped (D-NPC), duo-active-neutral-point-clamped (D-ANPC), and duo-neutral-point-piloted (D-NPP) multilevel voltage-sourced converter topologies. The D-NPC, D-ANPC, and D-NPP converters phase-leg is realized by adding low-frequency semiconductor power switches to their structures. This results in a substantial reduction in the number of the high-frequency pulsewidth-modulation insulated-gate bipolar transistors and clamping passive devices including diodes as well as flying-capacitors (FCs). Moreover, a drastic abatement in the total voltage rating and total stored energy of the FCs within the D-ANPC topology is achieved compared to the classic ANPC configuration. The experimental results are provided for D-NPC, D-ANPC, and D-NPP converters to validate the feasibility of their topology and modulation method for control of the multilevel converters. © 2013 IEEE.es
dc.description.urihttps://ieeexplore-ieee-org.recursosbiblioteca.unab.cl/document/8418843
dc.identifier.doi10.1109/JESTPE.2018.2859313
dc.identifier.issn2168-6777
dc.identifier.urihttps://repositorio.unab.cl/xmlui/handle/ria/24204
dc.language.isoenes
dc.publisherInstitute of Electrical and Electronics Engineers Inc.es
dc.rights.licenseAtribución 4.0 Internacional (CC BY 4.0)
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/deed.es
dc.subjectDiode abatementves
dc.subjectduo-active-neutral-point-clamped (D-ANPC) converteres
dc.subjectduo-neutral-point-clamped (D-NPC) converteres
dc.subjectduo-neutral-point-piloted (D-NPP) converteres
dc.subjectFC voltage decreasees
dc.subjectflying-capacitor (FC) energy reductiones
dc.subjectinsulated-gate bipolar transistor (IGBT) abatementes
dc.titleFundamental Circuit Topology of Duo-Active-Neutral-Point-Clamped, Duo-Neutral-Point-Clamped, and Duo-Neutral-Point-Piloted Multilevel Converterses
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IEEE Journal of Emerging and Selected Topics in Power Electronics Open AccessVolume 7, Issue 2, Pages 1224 - 1242June 2019 Article number 8418843
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